Some data types in Verilog, such as reg, are 4-state. This means that each bit can be one of 4 values: 0,1,x,z. With the "case equality" operator, ===, x's are compared, and the result is 1. With ==, the result of the comparison is not 0, as you stated; rather, the result is x, according to the IEEE Std (1800-2009), section 11.4.5 "Equality operators": For the logical equality and logical ...
What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example:
What is the difference between = and <= in Verilog? Asked 10 years, 2 months ago Modified 3 years, 4 months ago Viewed 113k times
verilog - What is the difference between single (&) and double ...
26 "<=" in Verilog is called non-blocking assignment which brings a whole lot of difference than "=" which is called as blocking assignment because of scheduling events in any vendor based simulators.
Double asterisk is a "power" operator introduced in Verilog 2001. It is an arithmetic operator that takes left hand side operand to the power of right hand side operand. In other words, X ** Y raises X to the power of Y. So in your case 2 ** NUM_TEST_BITS means 2 to the power of NUM_TEST_BITS.
Verilog bitwise or ("|") monadic Asked 12 years, 6 months ago Modified 12 years, 6 months ago Viewed 36k times
The lesson is to use the reg & wire types in classic Verilog, or the bit & logic types in modern Verilog, and size your signals appropriately. (Be warned, those types aren't equivalent)